Inter-device I/O (input/output) allows different system components to communicate to each other for operation of computing systems. Computing systems are used in any of a very wide array of consumer and commercial devices. Computing systems include memory subsystems to store and provide access to code and data executed by a processor of the computing system. I/O is important in memory subsystems to allow the transfer of data between the processor and the memory resources that store the code and data.
Specific memory technologies have standards that apply to timing associated with I/O that devices must meet to be considered compliant. DDR (double data rate) memory I/O systems provide phase compensation to lock a data signal with a clock or timing signal. One example of DDR I/O phase compensation is the use of a DLL (delay locked loop) that provides a variable amount of delay into a clock edge to adjust the timing of the clock signal. The amount of phase compensation per adjustment (often referred to in industry as “step size”) controls how quickly or slowly the DLL can lock on the correct phase timing. In one DDR implementation, there is a DLL lock specification that requires the DLL to lock within a specified number of clock cycles.
There is a tradeoff in the amount of phase compensation per adjustment: finer adjustments allow more precise locking, which improves signal quality, while coarser adjustments allow the DLL to lock within specification timing requirements. In a memory subsystem that is powered by a power supply with a lot of noise, finer adjustments can be lost in the noise, which can prevent the DLL from even “catching up” to the proper phase and obtaining a lock. Thus, there are advantages and disadvantages to both coarser phase adjustment size and finer phase adjustment size.
In addition to the limitations on phase adjustment size, traditional memory subsystem I/O designs also experience errors introduced by the lock position search mechanism. Most current digital DLL designs use a shift register design as the phase controller, and use binary search to determine the lock position. The binary search based on the shift register design can cause harmonic lock (locking on a harmonic instead of on the primary phase of the clock signal). The shift register state machine controller design is very complicated, which adds to overall system complexity and cost. The binary search is typically inflexible for tracking under noisy conditions.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.